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ADC1005S060 single 10 bits adc, up to 60 mhz rev. 03 ? 2 july 2012 product data sheet 1. general description the ADC1005S060 is a 10-bit high-speed lo w-power analog-to-digit al converter (adc) for professional video and other applications. it converts the analog input signal into 10-bit binary or gray coded digital words at a maximum sampling rate of 60 mhz. all digital inputs and outputs are transistor-transistor logic (ttl) and cmos compatible, although a low-level sine wave clock input signal is allowed. the device requires an external source to drive its reference ladder. 2. features ? 10-bit resolution (binary or gray code) ? sa mpling rate up to 60 mhz ? dc sampling allowed ? one clock cycle conversion only ? high signal-to-noise ratio over a large analog input frequency range (9.3 effective bits at 5 mhz full-scale input at f clk = 60 mhz) ? no missing cod es guaranteed ? in-r ange (ir) cmos output ? ttl and cmos levels compatible digital inputs ? 2 .7 v to 3.6 v cmos digital outputs ? low-lev el ac clock input signal allowed ? exte rnal reference voltage regulator ? powe r dissipation only 312 mw (typical) ? l ow analog input capacitance, no buffer amplifier required ? no samp le-and-hold circuit required 3. applications ? video data digitizing ? radar ? bar code scanners ? digit al instrumentation ? t ransient signal analysis ? ?? m odulators ? medical imaging
ADC1005S060_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 2 of 18 integrated device technology ADC1005S060 single 10 bits adc, up to 60 mhz 4. quick reference data table 1. quick reference data v cca = 4.75 v to 5.25 v; v ccd = 4.75 v to 5.25 v; agnd and dgnd shorted together; t amb = 0 ? c to 70 ? c; typical values measured at v cca = v ccd = 5 v; v cco = 3.3 v; v rb = 1.3 v; v rt = 3.7 v; c l = 10 pf and t amb = 25 ? c unless otherwise specified. symbol parameter conditions min typ max unit v cca analog supply voltage 4.75 5.0 5.25 v v ccd digital supply voltage 4.75 5.0 5.25 v v cco output supply voltage 2.7 3.3 3.6 v i cca analog supply current - 29 37 ma i ccd digital supply current - 33 40 ma i cco output supply current f clk = 60 mhz; ramp input - 0.5 2.0 ma inl integral non-linearity - ? 0. 8 ? 2.0 lsb dnl differential non-linearity - ? 0. 35 ? 0.9 lsb f clk(max) maximum clock frequency 60 - - mhz p tot total power dissipation f clk =60 mhz; ramp input - 312 411 mw 5. ordering information table 2. ordering information type number package name description version ADC1005S060ts ssop28 plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1
ADC1005S060_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 3 of 18 integrated device technology ADC1005S060 single 10 bits adc, up to 60 mhz 6. block diagram 12 dgnd n.c. 6 8 r lad 7 9 rb rm rt vi 11 v ccd 3 26 v cca 21 22 23 24 20 d4 d5 d6 d7 d8 19 18 25 2 d3 d2 17 d1 16 d0 d9 in-range latch cmos outputs latches clock driver 014aaa519 1 clk 10 15 oe gray tc ADC1005S060 13 v cco 4 agnd 14 ognd analog voltage input data outputs lsb msb ir output analog - to - digital converter cmos output 5, 27, 28 fig 1. block diagram
ADC1005S060_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 4 of 18 integrated device technology ADC1005S060 single 10 bits adc, up to 60 mhz 7. pinning information 7.1 pinning adc1005s 060ts clk n.c. tc n.c. v cca ir agnd d9 n.c. d8 rb d7 rm d6 vi d5 rt d4 oe d3 v ccd d2 dgnd d1 v cco d0 ognd gray 014aaa520 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 18 17 20 19 22 21 24 23 26 25 28 27 fig 2. pin configuration 7.2 pin description table 3. pin description symbol pin description clk 1 clock input tc 2 twos complement input (active low) v cca 3 analog supply voltage (5 v) agnd 4 analog ground n.c. 5 not connected rb 6 reference voltage bottom input rm 7 reference voltage middle input vi 8 analog voltage input rt 9 reference voltage top input oe 10 output enable input (active low) v ccd 11 digital supply voltage (2.7 v to 3.6 v) dgnd 12 digital ground v cco 13 supply voltage for output stages (2.7 v to 3.6 v) ognd 14 output ground gray 15 gray code input (active high) d0 16 data output; bit 0 (least significant bit (lsb)) d1 17 data output; bit 1 d2 18 data output; bit 2 d3 19 data output; bit 3
ADC1005S060_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 5 of 18 integrated device technology ADC1005S060 single 10 bits adc, up to 60 mhz 8. limiting values table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cca analog supply voltage [1] ? 0.3 +7.0 v v ccd digital supply voltage [1] ? 0.3 +7.0 v v cco output supply voltage [1] ? 0.3 +7.0 v ? v cc supply voltage difference v cca ? v ccd ? 0.1 +1.0 v v ccd ? v cco ; v cca ? v cco ? 0.1 +4.0 v v i input voltage referenced to agnd ? 0. 3 +7.0 v v i(clk)(p-p) peak-to-peak clock input voltage for switching; refe renced to dgnd - v ccd v i o output current - 10 ma t stg storage temperature ? 55 +150 ?c t amb ambient temperature ? 40 +85 ?c t j junction temperature - 150 ?c [1] the supply voltages v cca , v ccd and v cco may have any value between ? 0.3 v and +7.0 v provided that the supply voltage differences ? v cc are respected. 9. thermal characteristics table 5. thermal characteristics symbol parameter condition value unit r th(j-a) thermal resistance from junction to ambient in free air 110 k/w d4 20 data output; bit 4 d5 21 data output; bit 5 d6 22 data output; bit 6 d7 23 data output; bit 7 d8 24 data output; bit 8 d9 25 data output; bit 9 (most significant bit (msb)) ir 26 in-range data output n.c. 27 not connected n.c. 28 not connected table 3. pin description ?continued symbol pin description
ADC1005S060_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 6 of 18 integrated device technology ADC1005S060 single 10 bits adc, up to 60 mhz 10. characteristics table 6. characteristics v cca = 4.75 v to 5.25 v; v ccd = 4.75 v to 5.25 v; agnd and dgnd shorted together; t amb = 0 q c to 70 q c; typical values measured at v cca = v ccd = 5 v; v cco = 3.3 v; v rb = 1.3 v; v rt = 3.7 v; c l = 10 pf and t amb = 25 q c unless otherwise specified. symbol parameter conditions min typ max unit supplies v cca analog supply voltage 4.75 5.0 5.25 v v ccd digital supply voltage 4.75 5.0 5.25 v v cco output supply voltage 2.7 3.3 3.6 v ' v cc supply voltage difference v cca v ccd 0.2 - +0.2 v v cca v cco ; v ccd v cco 0.2 +2.55 v i cca analog supply current - 29 37 ma i ccd digital supply current - 33 40 ma i cco output supply current f clk = 60 mhz; ramp input - 0.5 2.0 ma p tot total power dissipation f clk = 60 mhz; ramp input - 312 411 mw inputs clock input clk (referenced to dgnd) [1] v il low-level input voltage 0 - 0.8 v v ih high-level input voltage 2 - v ccd v i il low-level input current v clk = 0.8 v 1 0 +1 p a i ih high-level input current v clk = 2 v - 2 10 p a c i input capacitance - 2 - pf inputs oe tc and gray (referenced to dgnd); see table 3 and 4 v il low-level input voltage 0 - 0.8 v v ih high-level input voltage 2 - v ccd v i il low-level input current v il = 0.8 v 1 - - p a i ih high-level input current v ih = 2.0 v - - 1 p a analog input vi (referenced to agnd) i il low-level input current v i = v rb = 1.3 v - 0 - p a
ADC1005S060_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 7 of 18 integrated device technology ADC1005S060 single 10 bits adc, up to 60 mhz i ih high-level input current v i = v rt = 3.7 v - 55 - p a y i input admittance f i = 5 mhz [2] r i, input resistance - 45 - k : c i, input capacitance 3 5 7 pf reference voltages for the resistor ladder; see table 7 v rb voltage on pin rb 1.2 1.3 2.2 v v rt voltage on pin rt 3.4 3.7 v cca 0.8 v v ref(dif) differential reference voltage v rt v rb 2.2 2.4 3.2 v i ref reference current v ref(dif) = 2.4 v - 17.6 - ma r lad ladder resistance - 136 - : tc rlad ladder resistor temperature coefficient - 253 - m : /k v offset offset voltage v ref(dif) = 2.4 v bottom [3] - 200 - mv top [3] - 190 - mv v i(a)(p-p) peak-to-peak analog input voltage v ref(dif) = 2.4 v [4] 1.95 2.01 2.10 v outputs digital outputs d9 to d0 and ir (referenced to ognd) v ol low-level output voltage i o = 1 ma 0 - 0.5 v v oh high-level output voltage i o = 1 ma v cco 0.5 - v cco v i oz off-state output current 0.5 v < v o < v cco 20 - +20 p a switching characteristics; clock input clk; see figure 4 [1] f clk(max) maximum clock frequency 60 - - mhz t w(clk)h high clock pulse width t amb = 25 q c 7.0 - - ns t w(clk)l low clock pulse width t amb = 25 q c 3.5 - - ns analog signal processing; f clk = 60 mhz linearity inl integral non-linearity ramp input - r 0.8 r 2.0 lsb dnl differential non-linearity ramp input - r 0.35 r 0.9 lsb table 6. characteristics ?continued v cca = 4.75 v to 5.25 v; v ccd = 4.75 v to 5.25 v; ag nd and dgnd short ed together; t amb = 0 q c to 70 q c; typical values measured at v cca = v ccd = 5 v; v cco = 3.3 v; v rb = 1.3 v; v rt = 3.7 v; c l = 10 pf and t amb = 25 q c unless otherwise specified. symbol parameter conditions min typ max unit
ADC1005S060_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 8 of 18 integrated device technology ADC1005S060 single 10 bits adc, up to 60 mhz e offset offset error middle code - r 1 - lsb e g gain error from device to device [5] - r 0.5 - % bandwidth b bandwidth full-scale sine wave [6] - 30 - mhz 75 % full-scale sine wave - 45 - mhz small signal at mid-scale; v i = r 10 lsb at code 512 - 700 - mhz t s(lh) low to high settling time full-scale square wave; see figure 6 [7] - 5 - ns t s(hl) high to low settling time full-scale square wave; see figure 6 [7] - 5 - ns harmonics d 2h second harmonic level f i = 5 mhz - 68 - db d 3h third harmonic level f i = 5 mhz - 67 - db thd total harmonic distortion f i = 5 mhz - 64 - db f i = 15 mhz - 57 - db sfdr spurious free dynamic range f i = 5 mhz - 72 db signal-to-noise ratio [8] s/n signal-to-noise ratio without harmonics; f i = 5 mhz - 58 - db without harmonics; f i = 15 mhz 53 57 - db effective bits [8] enob effective number of bits f i = 5 mhz - 9.3 - bits f i = 10 mhz - 8.9 - bits f i = 15 mhz - 8.8 - bits f i = 20 mhz - 8.6 - bits two-tone intermodulation [9] d im intermodulation suppression f clk = 60 mhz - 67 - db bit error rate ber bit error rate f i = 5 mhz; v i = r 16 lsb at code 512 - 10 13 - times/samples timing (f clk = 60 mhz; c l = 10 pf); see figure 4 [10] t d(s) sampling delay time - 0.7 2 ns t h(o) output hold time 4 - - ns t d(o) output delay time v cco = 2.7 v - 10 14 ns v cco = 3.3 v - 9 13 ns table 6. characteristics ?continued v cca = 4.75 v to 5.25 v; v ccd = 4.75 v to 5.25 v; ag nd and dgnd short ed together; t amb = 0 q c to 70 q c; typical values measured at v cca = v ccd = 5 v; v cco = 3.3 v; v rb = 1.3 v; v rt = 3.7 v; c l = 10 pf and t amb = 25 q c unless otherwise specified. symbol parameter conditions min typ max unit
ADC1005S060_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 9 of 18 integrated device technology ADC1005S060 single 10 bits adc, up to 60 mhz [1] the rise and fall times of the clock signal must not be less than 0.5 ns. [2] the input admittance is y i 1 r i ---- - j ? c i ++ [3] analog input voltages producing code 0 up to and including code 1023: a) v offset bottom is the difference between the analog input which produces data equal to 00 and the reference voltage on pin rb (v rb ) at t amb = 25 ? c. b) v offset top is the difference between the reference voltage on pin rt (v rt ) and the analog input which produces data outputs equal to code 1023 at t amb = 25 ? c . [4] to ensure the optimum linearity performance of such a converte r architecture the lower and upper extremities of the converte r reference resistor ladder are connected to pins rb and rt via offset resistors r ob and r ot as shown in figure 3. a) the current flowing into the resistor ladder is i v rt v rb ? r ob r l r ot ++ --------------------------------------- = and the full-scale input range at the converter, to cover code 0 to 1023 is v i r l i l ? r l r ob r l r ot ++ --------------------------------------- v rt v rb + ?? ? 0.8375 v rt v rb ? ?? ? == = b) since r l , r ob and r ot have similar behavior with respect to process and temperature variation, the ratio r l r ob r l r ot ++ --------------------------------------- will be kept reasonably constant from dev ice to device. consequently, variation of the output codes at a given input voltage de pends mainly on the difference v rt ? v rb and its variation with temperature and supply voltage. when several adcs are connected in parallel and fed with the same reference source, the matching between each of them is optimized. [5] e g v 1023 v 0 ? ?? v ip p ? ?? ? v ip p ? ?? ------------------------------------------------------ - 100 ? = [6] the analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. no glitches gre ater than 2 lsb, neither any significant attenuati on are observed in the reconstructed signal. [7] the analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale i nput (square wave signal) in order to sample the signal and obtain correct output data. [8] effective bits are obtained via a fast fourier transform (f f t) treatment taking 8000 acquisition points per equivalent funda mental period. the calculation takes into acc ount all harmonics and noise up to half th e clock frequency (nyqui st frequency). conversi on to signal-to-noise ratio: s/n = enob ? 6.02 + 1.76 db. [9] intermodulation measured relative to either tone with analog in put frequencies of 4.3 mhz and 4.5 mhz. the two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter. [10] output data acquisition: the output data is available af ter the maximum delay time of t d(o) . idt recommends the lowest possible output load. these parameters are guaranteed by characterization and not by production test. c l load capacitance - - 10 pf sr slew rate v cco = 2.7 v 0.2 0.3 - v/ns 3-state output delay times (f clk = 60 mhz; v cco = 3.3 v); see figure 5 t dzh float to active high delay time - 16 20 ns t dzl float to active low delay time - 30 34 ns t dhz active high to float delay time - 25 30 ns t dlz active low to float delay time - 23 27 ns table 6. characteristics ?continued v cca = 4.75 v to 5.25 v; v ccd = 4.75 v to 5.25 v; ag nd and dgnd short ed together; t amb = 0 ? ? ? symbol parameter conditions min typ max unit
ADC1005S060_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 10 of 18 integrated device technology ADC1005S060 single 10 bits adc, up to 60 mhz 11. additional information relating to table 6 014aaa521 rt rb rm r lad r ot r l r l r l r l i l r ob code 1023 code 0 fig 3. converter reference resistor ladder table 7. output coding and input voltage (typical values; referenced to agnd, v rb = 1.3 v, v rt = 3.7 v; binary/gray codes) code v i(a)(p-p) (v) ir binary outputs d9 to d0 gray outputs d9 to d0 underflow < 1.5 0 00 0000 0000 00 0000 0000 0 1.5 1 00 0000 0000 00 0000 0000 1 - 1 00 0000 0001 00 0000 0001 ? - ? ? ? 1022 - 1 11 1111 1110 10 0000 0001 1023 3.51 1 11 1111 1111 10 0000 0000 overflow > 3.51 0 11 1111 1111 10 0000 0000 table 8. output coding and input voltage (typical values; referenced to agnd; binary/twos complement codes) code v i(a)(p-p) (v) ir binary outputs d9 to d0 twos complement outputs d9 to d0 underflow < 1.5 0 00 0000 0000 10 0000 0000 0 1.5 1 00 0000 0000 10 0000 0000 1 - 1 00 0000 0001 10 0000 0001 ? - ? ? ? 1022 - 1 11 1111 1110 01 1111 1110 1023 3.51 1 11 1111 1111 01 1111 1111 overflow > 3.51 0 11 1111 1111 01 1111 1111
ADC1005S060_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 11 of 18 integrated device technology ADC1005S060 single 10 bits adc, up to 60 mhz table 9. tc mode selection tc oe d9 to d0 ir x 1 high impedance high impedance 0 0 active; two?s complement active 1 0 active; binary active table 10. gray mode selection gray oe d9 to d0 ir x 1 high impedance high impedance 0 0 active; binary active 1 0 active; gray active sample n + 1 sample n clk 014aaa522 sample n + 2 sample n + 1 sample n sample n + 2 50 % v ih v il vi data d0 to d9 high low 50 % data n + 1 data n data n ? 1 data n ? 2 t d(o) t w(clk)h t w(clk)l t d(s) t h(o) fig 4. timing diagram
ADC1005S060_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 12 of 18 integrated device technology ADC1005S060 single 10 bits adc, up to 60 mhz ADC1005S060 oe 10 pf 3.3 k s1 test v ccd t dlz v ccd t dzl dgnd t dzh t dhz dgnd 014aaa523 v ccd s1 50 % 50 % 50 % 10 % 90 % low low high high oe t dzh t dzl t dhz v ccd output data low output data high t dlz frequency on pin oe = 100 khz. fig 5. timing diagram and test condit ions of 3-state output delay time 014aaa524 code 1023 code 0 50 % 50 % clk vi t s(lh) t s(hl) 50 % 50 % 2 ns 2 ns 0.5 ns 0.5 ns fig 6. analog input settling time diagram
ADC1005S060_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 13 of 18 integrated device technology ADC1005S060 single 10 bits adc, up to 60 mhz 014aaa525 v cco d9 to d0 ir ognd v cca vi agnd 014aaa526 fig 7. d9 to d0 and ir outputs fig 8. vi analog input 014aaa527 v cco ognd oe tc gray v cca rt rm rb agnd 014aaa528 r l r l r l r l fig 9. oe gray and tc inputs fig 10. rb, rm and rt inputs v ccd clk 1.5 v dgnd 014aaa529 fig 11. clk input
ADC1005S060_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 14 of 18 integrated device technology ADC1005S060 single 10 bits adc, up to 60 mhz 12. application information 12.1 application diagrams (3) 33 adc1005s 060ts clk n.c. tc n.c. v cca ir agnd d9 n.c. d8 rb d7 rm d6 vi d5 rt d4 oe d3 v ccd d2 dgnd d1 v cco d0 ognd gray 014aaa530 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 18 17 20 19 22 21 24 23 26 25 28 27 100 nf 100 nf 100 nf 100 nf 100 nf 100 nf (2) (2) (2) agnd agnd agnd the analog and digital supplies should be separated and decoupled. a user manual is available that describes t he demon stration board that uses the version adc1004s030/040/050 family with an application environment. (1) rb, rm and rt are decoupled to agnd (2) decoupling capacitor for supplies must be placed close to the device. (3) this resistor is mandatory (33 ? is it s minimum value) and must be near the clock source. fig 12. application diagram 12.2 alternative parts the following alternative parts are also available: table 11. alternative parts type number description sampling frequency adc0804s030 single 8 bits adc [1] 30 mhz adc0804s040 single 8 bits adc [1] 40 mhz adc0804s050 single 8 bits adc [1] 50 mhz adc1003s030 single 10 bits adc, with in ternal reference regulator [1] 30 mhz adc1003s040 single 10 bits adc, with in ternal reference regulator [1] 40 mhz adc1003s050 single 10 bits adc, with in ternal reference regulator [1] 50 mhz
ADC1005S060_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 15 of 18 integrated device technology ADC1005S060 single 10 bits adc, up to 60 mhz [1] pin to pin compatible adc1004s030 single 10 bits adc [1] 30 mhz adc1004s040 single 10 bits adc [1] 40 mhz adc1004s050 single 10 bits adc [1] 50 mhz table 11. alternative parts type number description sampling frequency
ADC1005S060_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 16 of 18 integrated device technology ADC1005S060 single 10 bits adc, up to 60 mhz 13. package outline unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 1.25 7.9 7.6 0.9 0.7 1.1 0.7 8 0 o o 0.13 0.1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.2 mm maximum per side are not included. 1.03 0.63 sot341-1 mo-150 99-12-27 03-02-19 x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 11 4 28 15 0.25 y pin 1 index 0 2.5 5 mm scale ssop28: plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1 a max. 2 fig 13. package outline sot341-1 (ssop28)
ADC1005S060_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 17 of 18 integrated device technology ADC1005S060 single 10 bits adc, up to 60 mhz 14. revision history table 12. revision history document id release date data sheet status change notice supersedes ADC1005S060_3 20120702 product data sheet - ADC1005S060_2 ADC1005S060_2 20080813 product data sheet - ADC1005S060_1 modifications: corrections made to inl and dnl conditions in table ? 1. corrections made to several entries and notes in table ? 6. correction made to table description in table ? 7. correction made to column d9 to d0 in table ? 10. correction made to figure ? 8. correction made to figure ? 10. ADC1005S060_1 20080616 product data sheet - - 15. contact information for more information or sales office addresses, please visit: http://www.idt.com
ADC1005S060_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 18 of 18 integrated device technology ADC1005S060 single 10 bits adc, up to 60 mhz 16. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 thermal characteristics . . . . . . . . . . . . . . . . . . 5 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 6 11 additional informa tion relating to table 6 . . 10 12 application information . . . . . . . . . . . . . . . . . 14 12.1 application diagrams . . . . . . . . . . . . . . . . . . . 14 12.2 alternative parts . . . . . . . . . . . . . . . . . . . . . . . 14 13 package outline. . . . . . . . . . . . . . . . . . . . . . . . 16 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 17 15 contact information . . . . . . . . . . . . . . . . . . . . 17 16 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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